Sequential System Design

Sequential System Design

Unlike combinational circuits, where the output is determined solely by the current inputs, Sequential Logic Circuits have memory. The output of a sequential circuit depends on both the present inputs and the past sequence of inputs (the current state). To retain past information, sequential circuits employ memory elements (latches or flip-flops) and feedback loops where the output is routed back to the input.

1. The Clock Signal & Triggering

• Latches (Level-Triggered): State changes occur continuously as long as the clock/enable signal is at a specific voltage level (HIGH or LOW). Latches are transparent.
• Flip-Flops (Edge-Triggered): State changes occur only at the exact moment the clock transitions from LOW to HIGH (Positive Edge) or HIGH to LOW (Negative Edge). This precise timing prevents unstable feedback loops.

2. Flip-Flops (The Memory Building Blocks)

2.1 SR (Set-Reset) Flip-Flop

The basic memory cell.

• S = 1, R = 0: Sets the output to $1$.
• S = 0, R = 1: Resets the output to $0$.
• S = 0, R = 0: Memory state (Holds $Q_n$).
• S = 1, R = 1: Invalid/Forbidden state (causes unpredictable behavior).
• Characteristic Equation: $$Q_{n+1} = S + R'Q_n$$ (Valid only if $SR = 0$)

2.2 D (Data / Delay) Flip-Flop

Created by adding an inverter between the S and R inputs. It ensures that S and R are never equal, eliminating the invalid state. The output simply follows the input at the clock edge.

• Characteristic Equation: $$Q_{n+1} = D$$

2.3 JK Flip-Flop

• J = 1, K = 1: Toggles the output ($Q_{n+1} = Q_n'$).
• Characteristic Equation: $$Q_{n+1} = JQ_n' + K'Q_n$$ The Race-Around Condition: In a level-triggered JK Latch, if $J=1, K=1$, the output will continuously toggle back and forth as long as the clock is HIGH, leading to an unpredictable final state. This is called the Race-Around condition. It is solved by using Edge-Triggering or a Master-Slave configuration.

2.4 T (Toggle) Flip-Flop

• T = 0: Memory state.
• T = 1: Toggles the state.
• Characteristic Equation: $$Q_{n+1} = T \oplus Q_n$$

3. Shift Registers

1. SISO (Serial-In, Serial-Out): Data enters one bit at a time and exits one bit at a time. Acts as a time delay.
2. SIPO (Serial-In, Parallel-Out): Converts a serial data stream into a parallel format.
3. PISO (Parallel-In, Serial-Out): Converts parallel data into a serial stream (e.g., for UART transmission).
4. PIPO (Parallel-In, Parallel-Out): Standard memory buffer. Fastest read/write.

4. Counters

4.1 Asynchronous (Ripple) Counters

• Advantage: Simple hardware design.
• Disadvantage: Slower. The propagation delays of each flip-flop add up (ripple effect). The maximum clock frequency is limited by $$f_{max} = \frac{1}{n \times t_{pd}}$$

4.2 Synchronous Counters

• Advantage: Extremely fast, as there is no cumulative propagation delay.
• Disadvantage: Complex combinational logic is required to determine the inputs for each flip-flop.

4.3 Special Shift-Counters

• Ring Counter: A circular shift register where the output of the last flip-flop is fed directly back to the first. If initialized with a single '1', it acts as a sequencer. MOD = $n$.
• Johnson (Twisted-Ring) Counter: The inverted output of the last flip-flop is fed back to the first. MOD = $2n$.